DMTS, DRAM Architecture

Responsibilities:
Define next-generation DRAM system architectures across performance, capacity, RAS, and telemetry
Lead cross-stack co-optimization across silicon, package, module, board, and system
Architect advanced RAS and telemetry features and translate system requirements into silicon
Drive long-range memory technology strategy and influence industry standards
Serve as a senior technical interface to customers, executives, and partners

Minimum Qualifications:
Bachelor's degree or equivalent practical experience in EE, CE, CS, or related field
Extensive hands-on experience in DRAM or memory systems architecture
Deep understanding of DRAM timing, signaling, power, and reliability mechanisms
Proven ability to translate system requirements into silicon architecture
Experience applying AI or LLMs for engineering efficiency

Preferred Qualifications:
Master's degree or PhD in a related technical field
Recognized technical leadership across multiple products or teams
Experience engaging tier-1 customers and ecosystem partners
History of architectural innovations adopted into production

Skills Required
Bachelor's degree in EE, CE, CS, or related field
Extensive hands-on experience in DRAM or memory systems architecture
Deep understanding of DRAM timing, signaling, power, and reliability mechanisms
Proven ability to translate system requirements into silicon architecture